module register # (parameter N=4)(in, load, q, clk, reset);
    input clk, reset;
    input [N-1:0] in;
    input load;
    output reg [N-1:0] q;
    always @ (posedge clk or posedge reset)
    begin
        if (reset) q <= 0;
        else if (load) q <= in;
    end
endmodule
